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| (R) L6386 HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER HIGH VOLTAGE RAIL UP TO 600V dV/dt IMMUNITY +- 50 V/nsec iN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 400 mA SOURCE, 650 mA SINK SWITCHING TIMES 50/30 nsec RISE/FALL WITH 1nF LOAD CMOS/TTL SCHMITT TRIGGER INPUTS WITH HYSTERESIS AND PULL DOWN UNDER VOLTAGE LOCK OUT ON LOWER AND UPPER DRIVING SECTION INTEGRATED BOOTSTRAP DIODE OUTPUTS IN PHASE WITH INPUTS DESCRIPTION The L6386 is an high-voltage device, manufactured with the BCD "OFF-LINE" technology. It has a Driver structure that enables to drive indeBLOCK DIAGRAM SO14 DIP14 ORDERING NUMBERS: L6386D L6386 pendent referenced Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. BOOTSTRAP DRIVER 14 VCC 4 UV DETECTION UV DETECTION Vboot H.V. R R HVG DRIVER 13 OUT VCC 12 LVG LVG DRIVER 9 PGND 8 VREF + 5 DIAG TO LOAD HVG CBOOT HIN 3 LEVEL SHIFTER LOGIC S SD 2 LIN 1 SGND 7 6 CIN D97IN520D July 1999 1/10 L6386 ABSOLUTE MAXIMUM RATINGS Symbol Vout Vcc Vboot Vhvg Vlvg Vi Vdiag Vcin dVout/dt Ptot Tj Ts Output Voltage Supply Voltage Floating Supply Voltage Upper Gate Output Voltage Lower Gate Output Voltage Logic Input Voltage Open Drain Forced Voltage Comparator Input Voltage Allowed Output Slew Rate Total Power Dissipation (Tj = 85 C) Junction Temperature Storage Temperature Parameter Value -3 to Vboot - 18 - 0.3 to +18 -1 to 618 - 1 to Vboot -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 50 750 150 -50 to 150 Unit V V V V V V V V V/ns mW C C Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 900V (Human Body Model) PIN CONNECTION LIN SD HIN VCC DIAG CIN SGND 1 2 3 4 5 6 7 D97IN521A 14 13 12 11 10 9 8 Vboot HVG OUT N.C. N.C. LVG PGND THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO14 165 DIP14 100 Unit C/W PIN DESCRIPTION N. 1 2 3 4 5 6 7 8 9 10, 11 12 13 14 Name LIN SD (*) HIN VCC DIAG CIN SGND PGND LVG (*) N.C. OUT HVG (*) Vboot Type I I I I O I Function Lower Driver Logic Input Shut Down Logic Input Upper Driver Logic Input Low Voltage Supply Open Drain Diagnostic Output Comparator Input Ground Power Ground Low Side Driver Output Not Connected Upper Driver Floating Driver High Side Driver Output Bootstrapped Supply Voltage O O O (*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA), with VCC >3V. This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 2/10 L6386 RECOMMENDED OPERATING CONDITIONS Symbol Vout VbootVout fsw Vcc Tj 4 Pin 12 14 Parameter Output Voltage Floating Supply Voltage Switching Frequency Supply Voltage Junction Temperature -45 HVG,LVG load CL = 1nF Test Condition Min. Note1 Note1 Typ. Max. 580 17 400 17 125 Unit V V kHz V C Note 1: if the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V. ELECTRICAL CHARACTERISTICS AC Operation (Vcc = 15V; Tj = 25C) Symbol ton toff tsd tr tf Pin 1.3 vs 9, 13 2 vs 9,13 13,9 13,9 Parameter High/Low Side Driver Turn-On Propagation Delay High/Low Side Driver Turn-Off Propagation Delay Shut Down to High/Low Side Propagation Delay Rise Time Fall Time Test Condition Vout = 0V Vout = 0V Vout = 0V CL = 1000pF CL = 1000pF Min. Typ. 110 105 105 50 30 Max. 150 150 150 Unit ns ns ns ns ns DC Operation (Vcc = 15V; Tj = 25C) Symbol Pin Parameter Low Supply Voltage Section Vcc 4 Supply Voltage Vccth1 Vcc UV Turn On Threshold Vccth2 Vcc UV Turn Off Threshold Vcchys Vcc UV Hysteresis Iqccu Undervoltage Quiescent Supply Current Iqcc Quiescent Current Bootstrapped Supply Section Vboot 14 Bootstrapped Supply Voltage Vbth1 Vboot UV Turn On Threshold Vbth2 Vboot UV Turn Off Threshold Vbhys Vboot UV Hysteresis Iqboot Vboot Quiescent Current Ilk Leakage Current Rdson Bootstrap Driver on Resistance (*) Driving Buffers Section Iso 9, 13 High/Low Side Driver Short Circuit Source Current Isi High/Low Side Driver Short Circuit Sink Current Logic Inputs Vil 1,2,3 Low Level Logic Threshold Voltage Vih High Level Logic Threshold Voltage Iih High Level Logic Input Current Iil Low Level Logic Input Current (*) RDSON is tested in the following way: RDSON = Test Condition Min. Typ. Max. 17 12.5 10.5 Unit V V V V A A V V V V A A mA mA 11.5 9.5 Vcc 11V Vcc = 15V 12 10 2 200 250 320 17 12.9 10.7 200 10 10.7 8.8 Vout = Vboot Vout = Vboot = 600V Vcc 12.5V; Vin = 0V VIN = Vih (tp < 10s) 300 500 11.9 9.9 2 125 400 650 1.5 3.6 VIN = 15V VIN = 0V 50 70 1 V V A A (VCC - VCBOOT1) - (VCC - VCBOOT2) I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. 3/10 L6386 DC OPERATION (continued) Symbol Vio Iio Vol Vref 6 2 Pin Parameter Input Offset Voltage Input Bias Current Open Drain Low Level Output Voltage, Iod = -2.5mA Comparator Reference voltage 0.460 0.5 Vcin 0.5 Test Condition Min. -10 0.2 0.8 0.540 Typ. Max. 10 Unit mV A V V Sense Comparator Figure 1. Timing Waveforms HIN LIN SD HOUT LOUT VREF VCIN DIAG Note: SD active condition is latched until next negative IN edge. D97IN522A Figure 2. Typical Rise and Fall Times vs. Load Capacitance time (nsec) 250 200 Tr 150 Tf 100 50 0 D99IN1054 Figure 3. Quiescent Current vs. Supply Voltage Iq (A) 104 D99IN1057 103 102 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25C Tamb 0 2 4 6 8 10 12 14 16 VS(V) 4/10 L6386 BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 4a). In the L6386 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 4b An internal charge pump (fig. 4b) provides the DMOS driving voltage . The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. CBOOT selection and charging: To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : CEXT = Qgate Vgate supply 1C to CEXT. This charge on a 1F capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Vdrop = IchargeRdson Vdrop = Qgate Tcharge Rdson The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200A, so if HVG TON is 5ms, CBOOT has to Figure 4. Bootstrap Driver. D BOOT where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5s. In fact: Vdrop = 30nC 125 ~ 0.8V 5s Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. VS VBOOT H.V. HVG VS VBOOT H.V. HVG C BOOT VOUT TO LOAD CBOOT VOUT TO LOAD LVG LVG a b D99IN1056 5/10 L6386 Figure 5. Turn On Time vs. Temperature 250 Figure 8. VBOOT UV Turn On Threshold vs. Temperature 15 @ Vcc = 15V 200 14 13 Vbth1 (V) 12 11 10 9 8 Typ. @ Vcc = 15V Ton (ns) 150 Typ. 100 50 0 -45 -25 0 25 50 Tj (C) 75 100 125 7 -45 -25 0 25 50 Tj (C) 75 100 125 Figure 6. Turn Off Time vs. Temperature 250 Figure 9. VBOOT UV Turn Off Threshold vs. Temperature 15 @ Vcc = 15V 200 Toff (ns) 150 100 50 0 -45 -25 0 25 50 Tj (C) 75 100 125 Typ. 14 13 Vbth2 (V) 12 11 10 9 8 7 -45 -25 0 25 50 Tj (C) Typ. @ Vcc = 15V 75 100 125 Figure 7. Shutdown Time vs. Temperature 250 Figure 10. VBOOT UV Hysteresis 3 @ Vcc = 15V 200 tsd (ns0 150 100 50 0 -45 -25 0 25 50 Tj (C) 75 100 125 Typ. @ Vcc = 15V 2.5 Vbhys (V) Typ. 2 1.5 1 -45 -25 0 25 50 Tj (C) 75 100 125 6/10 L6386 Figure 11. Vcc UV Turn On Threshold vs. Temperature 15 14 Figure 14. Output Source Current vs. Temperature 1000 @ Vcc = 15V 800 current (mA) 600 Typ. 13 12 11 10 9 -45 -25 0 25 50 Tj (C) 75 100 125 Typ. Vccth1(V) 400 200 0 -45 -25 0 25 50 Tj (C) 75 100 125 Figure 12. Vcc UV Turn Off Threshold vs. Temperature 12 11 10 Typ. Figure 15. Output Sink Current vs. Temperature 1000 @ Vcc = 15V 800 current (mA) 600 400 200 0 -45 Typ. Vccth2(V) 9 8 7 -45 -25 0 25 50 75 100 125 -25 0 Tj (C) 25 50 Tj (C) 75 100 125 Figure 13. Vcc UV Hysteresis vs. Temperature 3 2.5 Vcchys (V) Typ. 2 1.5 1 -45 -25 0 25 50 Tj (C) 75 100 125 7/10 L6386 DIM. MIN. a1 B b b1 D E e e3 F I L Z 1.27 0.51 1.39 mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 15.24 7.1 5.1 3.3 2.54 0.050 0.055 inch TYP. MAX. OUTLINE AND MECHANICAL DATA 0.065 0.020 0.010 0.787 0.335 0.100 0.600 0.280 0.201 0.130 0.100 DIP14 8/10 L6386 mm MIN.. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 8.55 5.8 1.27 7.62 4 5.3 1.27 0.68 8 (max.) 0.150 0.181 0.016 0.35 0.19 0.5 45 (typ.) 8.75 6.2 0.336 0.228 0.050 0.300 0.157 0.209 0.050 0.027 0.344 0.244 0.1 TYP. MAX.. MIN.. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 inch TYP.. MAX.. 0.069 0.009 0.063 0.018 0.010 DIM. OUTLINE AND MECHANICAL DATA SO14 (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 9/10 L6386 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 10/10 |
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